Exemplary embodiments of the present invention relate to an image processing system, and more particularly, to an image processing system having an on-chip test mode for column-parallel analog-to-digital converters (ADCs).
Proliferation of complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) in consumer markets has been accelerated by the adoption of CIS in many popular consumer electronics applications including, e.g., mobile handsets. This trend, together with the rapid growth in smart phone markets, has led manufacturers and consumers to desire apparently ever-increasing resolutions in their CIS applications. In this context, CIS designers have remained constrained by issues relating to die sizes and aspect ratios, costs, power consumption, and others.
As sensor resolution increases, operation of the sensors in desired frame rates, e.g., a full HD frame rate, involves higher data conversion rates. Many typical applications of high resolution sensors employ single-slope column-parallel analog-to-digital converters (ADCs) at least to achieve these higher data conversion rates while dissipating low power. For example, in comparison to competing architectures, like serial pipeline ADC architectures, the column-parallel ADC architecture may achieve lower read noise, and thus higher dynamic range, due to reduced bandwidth circuit readouts for each column's ADC.
Typical single-slope column-parallel ADCs may tend to experience both row-wise and column-wise noises from various sources. For example, some row-wise noise may result from power supply movement, and some column-wise noise which is so called column fixed-pattern noise (CFPN) may result from device and parasitic mismatch. The various types of noise may cause undesirable effects including, e.g., limitations on the sensitivity of the CIS, visible artifacts in the CIS output, and the like. Thus, it may be desirable to provide techniques for addressing these row-wise and/or column-wise noise sources.
Meanwhile, the performance of column-parallel ADCs employed in a CIS may be tested by directly inputting an external analog signal to the column-parallel ADCs and obtaining a digital output value, or by directly irradiating light to a pixel array.
However, the method of directly inputting an external analog signal from the outside to the ADCs has limitation in the test itself, and the method of irradiating light to a pixel array takes much time to test the performance of the column-parallel ADCs because the intensity of the radiation should be controlled in several steps to acquire an accurate test result.